The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use either a combination of logic gates or a look-up table to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to a specific logic operations. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
A typical design cycle for determining the configuration of a programmable device includes starts with an extraction phase, followed by a synthesis phase, a fitting phase, and an assembly phase. The extraction phase takes a user design, typically expressed in a hardware description language such as verilog or VHDL, and produces a set of logic gates implementing the user design. In the synthesis phase, the set of logic gates is permutated over the hardware architecture of the programmable device in order to match elements of the user design with corresponding portions of the programmable device. The fitting or routing phase assigns the various portions of the user design to specific logic cells and functional blocks of the programmable device, taking care to minimize the length and number of connections needed by the switching circuit. In the assembly phase, a configuration file defining the programmable device configuration is created. The configuration can then be loaded into a programmable device to implement the user design.
Many programmable devices implement logic cells as one or more configurable look-up tables for implementing logic functions, one or more registers for storing data values, and some additional hardware for secondary functions, such as load and clear functions. The load and clear functions reset the value of a logic cell register to zero or to an initial value and are typically used for initializing a logic cell, for example at system start-up or at the beginning of a loop. The load and clear hardware is also used in arithmetic chains. This hardware is typically unused for other applications.
In theory, the secondary hardware in logic cells can also be used to implement other logic functions, thereby decreasing the number of gates that need to be implemented with look-up tables or other hardware and improving the performance and efficiency of the programmable device. As the load and clear hardware is typically unused outside of a few narrow applications, implementing logic functions in this manner is “free” and does not consume additional device resources.
However, secondary hardware is rarely exploited for this purpose because of the difficulties in matching dissimilar portions of a user design with the structure of the load and clear hardware. Prior approaches, such as design templates matching user design patterns with logic cell hardware, typically miss user designs that trivially deviate from the design templates and require user designs to rigidly adhere to complex design rules. Furthermore, when secondary hardware is used for too much of a user design, the routing phase will require an excess amount of connections from the switching circuit, resulting in a net decrease in performance and efficiency. Additionally, many user designs can be implemented with secondary hardware in a number of different alternative configurations. Often, the choice of configuration is incompatible with neighboring logic cells and can result in excess and inefficient connections from the switching circuit.
It is therefore desirable for a system and method of synthesis to efficiently exploit the secondary hardware of logic cells in implementing a wide variety of user designs, regardless of the similarity between the user design and the structure of the secondary hardware. It is further desirable that the system and method of synthesis does not detrimentally impact the amount of connections required by the switching circuit in the fitting phase.